1. Field of the Invention
This invention relates generally to testing of integrated circuits with scan paths and particularly relates to testing integrated circuits with parallel scan distributors and collectors controlled by a controller that includes a state machine.
2. Description of the Related Art
Cost effective testing of today""s complex integrated circuits is extremely important to semiconductor manufacturers from a profit and loss standpoint. The increases in complexity of state-of-the-art integrated circuits is being accompanied by an ever increasing difficulty to test the integrated circuits. New test techniques must be developed to offset this increasing integrated circuit test cost, otherwise further advancements in future integrated circuit technology may be blocked. One emerging technology that is going to accelerate the complexity of integrated circuits even more is intellectual property cores. These cores will provide highly complex pre-designed circuit functions such as; DSPs, CPUs, I/O peripherals, memories, and mixed signal A/D and D/A functions. These cores will exist in a library and can be selected and placed in an integrated circuit quickly to provide a complex circuit function. The low cost testing of integrated circuits that contain highly complex core functions will be a significant challenge
The disclosed circuits provide a description of a controller for use with the parallel scan distributor and collector circuits. The controller has a test control register, a test control state machine and a multiplexer. The controller also has inputs and outputs for connection to additional controllers in a hierarchical or parallel arrangement. The controller is also programmable to provide different types of test control for testing different types of circuits.
The disclosed parallel scan distributor and collector circuits provide a low power method of scan testing combinational logic within an IC by allowing scan test communication to occur over a larger number of shorter length scan paths.
With a synchronizer and delay circuit, the disclosed test circuits can further reduce the power needed to test the integrated circuits. The test circuits disclosed can be used to test functional combinatorial logic, random access memory, and digital to analog and analog to digital circuitry. Conventional IEEE 1149.1 test access port or TAP circuits can be modified to operate with the disclosed scan distributor and collectors circuits and controllers.